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package edu.marist.cs.os.g3.processors;

/**
 *
 * @author Intern
 */
public class CPU {
    public static enum Mode { MASTER, SLAVE };    
    public Mode mode;
    
    /**
     * Instruction register
     */
    public String IR = "    ";
    /**
     * Instruction counter
     */
    public int IC = 0;
    
    /**
     * Register C: True or False
     */
    public boolean C = false;;
    
    /**
     * The accumulator R
     */

    public String R = "    ";
    
    /**
     * Page Table Register
     */
    public int PTR = -1;
    
    /**
     * I/O Interrupt
     * Values:
     * 0: Nothing
     * Rest are a sum of:
     * 1 - Channel 1 done
     * 2 - Channel 2 done
     * 4 - Channel 3 done
     * 
     * or can be thought of as a binary code:
     * (Channel 3)(Channel 2)(Channel 1)
     */
    public int IOI = 0;
    
    /**
     * Program Interrupt
     * Thrown in Slave Mode
     * Values:
     * 0: Nothing
     * 1: Operation Error
     * 2: Operand Error
     * 3: Page Fault
     */
    public int PI = 0;
    
    /**
     * Timer Interrupt
     * Values:
     * 0: Nothing
     * 1: Time Slice Up
     * 2: Time Limit Exceeded
     */
    public int TI = 0;
    
    /**
     * Supervisor Interrupt
     * Values:
     * 0: Nothing
     * 1: GD
     * 2: PD
     * 3: H   
     */
    public int SI = 0;
}
